IBM and Siemens have announced a research collaboration to advance IBM’s nanostack architecture, a three-dimensional transistor design for the next era of semiconductor scaling that IBM unveiled earlier in 2026. The collaboration is best understood as a bet on timing. Leading-edge chipmakers are reaching the practical limits of shrinking transistors in two dimensions, and the industry’s roadmap now depends on moving into the third. IBM is trying to establish the architecture, and the tooling, before the transition becomes urgent — which is why it brings design-software expertise into a research programme years ahead of any product. The collaboration pairs IBM’s semiconductor device research with Siemens’ expertise in electronic design automation (EDA), process simulation, lithography optimisation and advanced manufacturing software.
The goal is to develop the design and simulation capabilities needed to prepare nanostack — and the generations that follow it — for manufacturing, extending the work beyond the current 7 angstrom node. The two companies will build advanced virtual models to predict performance, optimise designs and surface fabrication problems before anyone builds silicon.
The framing from both sides is about co-optimisation. IBM’s Huiming Bu, vice president of silicon technology R&D, describes nanostack as a scalable platform “designed to shift device scaling from 2D to 3D,” a path for the logic scaling needed to support AI over the coming decade. Siemens’ Ankur Gupta, executive vice president of the EDA IC portfolio, frames the challenge as one where “scaling semiconductors into the angstrom era demands tightly coupled co-optimisation between device physics, EDA design and manufacturing software, and manufacturing.”
What nanostack is
Nanostack is the successor IBM proposes to nanosheets, the gate-all-around transistor technology IBM invented and which reached production at 3 nm and 2 nm nodes. Instead of placing n-type and p-type transistors side by side, nanostack stacks them, one above the other, using 3D sequential integration. The architecture also changes how circuits are laid out. With n-type and p-type devices stacked rather than side by side, a standard cell’s footprint shrinks, but the electrical relationships between the two layers — resistance, capacitance, thermal coupling — become part of the design problem rather than an afterthought. That shift is what makes new design tools necessary rather than optional. The design vertically stacks and staggers the transistors, and because the two layers can use different channel materials, engineers can optimise each transistor type independently.
IBM’s published figures are striking: nearly 100 billion transistors on a chip the size of a fingernail, roughly double the density of its 2 nm chip, with projections of up to 50% more performance or 70% greater energy efficiency, plus 40% scaling in SRAM. The SRAM result matters for AI: on-chip memory access is a known bottleneck, and denser memory helps chips feed data-hungry accelerators.
Why EDA is the bottleneck
The interesting thing about the collaboration is who is in it. IBM demonstrated nanostack’s viability earlier this year; what stands between that demonstration and a product is not a single device breakthrough but a set of design and manufacturing capabilities that do not yet exist. When transistors stack in three dimensions, several assumptions baked into conventional chip design break: where heat travels, how timing behaves, how engineers extract parasitics, and how the two device types interact.
That is why an EDA vendor is central rather than incidental. Designers need models, design rules and standard-cell libraries before they can design anything for a process, and IBM has said it plans to release an early research process design kit for the 7 angstrom nanostack in the first quarter of 2027. Siemens’ contribution — simulation, virtual modelling, lithography optimisation — targets design-technology co-optimisation early, so that foundries and fabless designers can evaluate the architecture long before it is manufacturable. That co-optimisation is increasingly how leading-edge development works.
As features approach atomic dimensions, the cost of discovering a physics problem late in the flow has become prohibitive, so research houses pull tool vendors in early. The nanostack collaboration follows that pattern: rather than wait for a manufacturable process, IBM and Siemens are trying to model the architecture’s behaviour while it is still being defined. In that sense the collaboration is less about inventing nanostack than about making it designable.
The manufacturing hurdles
The obstacles are well documented and substantial. Nanostack bonds two wafers with a thin dielectric layer, a process that requires wafer-scale alignment accurate to a nanometre or two and a fabrication flow that keeps temperatures below roughly 400 °C so the lower layer’s connections survive. Because the chip now has two layers of transistors, a defect in either can fail the whole device, which raises yield risk and cost. Wiring is harder too, since connections must span multiple levels of transistors, and heat must be conducted out of an increasingly dense stack — a challenge IBM acknowledges it is still working on.
Independent comment reinforces how demanding this is. A materials scientist quoted in MIT Technology Review noted the wafer alignment tolerances are impressive and that stacking doubles the failure modes. The same analysis points out that “0.7 nanometre” or “7 angstrom” is a generation name, not a physical measurement: the smallest features on the chip are around 14 to 20 nanometres, similar to today’s state of the art, and the density gain comes from packing transistors more tightly rather than shrinking them.
The Thermal Question
The thermal question is the one IBM flags most openly. Stacking transistors concentrates heat in a smaller volume, and the bonding layer between the two wafers must both insulate electrically and conduct heat away. IBM’s researchers describe thin dielectric bonding with thermally conductive material as one of the capabilities still needed before the architecture is ready for industry adoption, alongside 3D metrology and inspection. There is also a supply-chain dimension. Moving to a stacked architecture changes what fabs must buy and how they build lines, from high-aspect-ratio etching tools to atomic-layer deposition equipment and advanced back-end-of-line metallisation. For equipment makers, semiconductor scaling into the third dimension is a new product cycle; for foundries, it is a capital and yield-risk decision they will make cautiously. The competitive field for semiconductor scaling is crowded.
IBM’s approach is a form of complementary FET (CFET), and Intel, Samsung, TSMC and the Belgian lab Imec are all pursuing CFET designs. IBM’s distinction is the staggered layout, which it says simplifies wiring; independent observers credit it with improving alignment precision. IBM also expects to lean on High NA EUV lithography at its Albany research facility, developed with partners including ASML, Lam Research, Tokyo Electron and SCREEN.
For the wider industry, the stakes extend beyond one company’s roadmap. If nanostack or a rival CFET design becomes the next mainstream transistor, the transition will ripple through foundries, equipment suppliers and EDA vendors, all of which will need to retool. IBM’s decision to release an early design kit is an attempt to seed that ecosystem before the architecture is proven at scale.
What to watch
Three things will show whether nanostack advances. First, whether the early process design kit arrives on schedule in early 2027, since a PDK that designers can actually use is the clearest sign the architecture is becoming an ecosystem rather than a lab result. Second, whether IBM or its partners publish yield and reliability data, the numbers that separate a demonstration from a manufacturable process. Third, whether the EDA tools Siemens is adapting produce designs that work, which would confirm the co-optimisation thesis the collaboration rests on.
A fourth signal is costing. Nanostack’s density gains are compelling on paper, but the economics of semiconductor scaling depend on yield and on the cost per working transistor, not on density alone. Until the industry sees those numbers, the architecture remains a promising research result rather than a settled direction.
What the collaboration does and doesn’t establish
It establishes a research partnership between IBM and Siemens, a defined scope covering simulation, lithography and EDA, and an intent to build virtual models for nanostack and its successors. It does not establish a production timeline, yield figures, cost, or that foundries will adopt nanostack rather than a competing CFET approach.
The honest summary: this is the unglamorous half of a chip breakthrough, and arguably the harder half. None of this is unusual for a breakthrough at this stage; it is the normal shape of leading-edge semiconductor research, where a demonstration is a beginning rather than an end, and where the design and manufacturing work that follows decides whether the invention matters. IBM has shown it can build nanostack, a milestone in semiconductor scaling; the collaboration is about making it designable and manufacturable at scale, which is where most leading-edge architectures either succeed or stall.
The node name invites scepticism — “7 angstrom” is a label, not a measurement — and production remains around five years out on IBM’s own estimate. But the strategic logic is sound: as 2D semiconductor scaling runs out, the industry’s next decade depends on moving into the third dimension, and that transition needs design tools as much as it needs transistors.
Editor’s Note: This article draws on the IBM/Siemens release and IBM’s published research materials, the VLSI papers, and independent coverage and analysis by EE Times, MIT Technology Review, Ars Technica, Science/AAAS, eeNews Europe and Semiconductor Insider. The architecture, collaboration scope and projections are as describe by the companies; performance and efficiency figures are projections, no yield or production data was disclose, and the “7 angstrom” node name is a generation label rather than a physical dimension.