Chip Design AI: Cadence Maestro vs Synopsys’s OpenAI Bet

Cadence Built Its Own Chip Design Models. Synopsys Bet on OpenAI Instead

The two EDA leaders have split on where a customer’s design data goes. Cadence’s 30 per cent claim is measured against its own untrained base model.

Cadence announced Maestro, a portfolio of domain-specialised AI models that power its four AI Super Agents across chip and system design, and the announcement reads best beside a competitor’s. On 30 September, Synopsys said it would develop a model with OpenAI and share revenue with the lab, running on OpenAI-hosted infrastructure. Four weeks later, Cadence went the other way: open weights, a model-agnostic portfolio built partly on NVIDIA’s Nemotron, and the option to run everything behind a customer’s own firewall.

The split matters because of what chipmakers hold. A design file is the most closely guarded asset a semiconductor company owns, and where it goes during fine-tuning has become a purchasing decision rather than a technical footnote, and the two vendors have now answered it differently.

What Maestro actually is

The architecture is worth stating precisely. Maestro is not a single model but a portfolio spanning sizes and architectures: domain-specialised post-trained language models, trained decision models and reusable agent skills. It sits underneath Cadence’s four AI Super Agents, ChipStack for design and verification, ViraStack for custom and analog, InnoStack for digital implementation and AuraStack for packaging and printed circuit boards, and connects them to the company’s electronic design automation and system design automation tools.

The mechanism that distinguishes it is the reward signal. Cadence trains with reinforcement learning, but the reward comes from its own deterministic solvers and evaluation harnesses scoring agent output against engineering objectives, constraints and ground truth. That is a different proposition from learning from human preference. A solver can tell an agent whether a design closes timing, whether it meets a power budget, whether it fits an area constraint, and it can do so thousands of times without a person in the loop. NVIDIA’s Tim Costa described the arrangement as grounding reinforcement learning in feedback from EDA tools and deterministic solvers, which is a fair account of why the loop can run unattended.

The customer count is modest and honest. Cadence describes about a dozen engagements for Maestro, and its July earnings call put ChipStack above 20 customer engagements and ViraStack above 25. Those are pilots and early deployments rather than a market, and Cadence describes them as engagements rather than customers in production at scale.

The measurement gap

The headline numbers need care. Cadence reports up to 30 per cent improvement in quality of results and up to five times greater token efficiency against a general-purpose foundation model, from initial design-workflow results. Two things about that comparison matter. The first is that quality of results in chip design normally means power, performance and area, and Cadence has not said which of those the 30 per cent measures or how it weights them. A design that gains 30 per cent on area while losing power has not obviously improved.

The second is the baseline. Asked what general-purpose model it compared against, Cadence said it was the open-source model Maestro started from before training, and declined to name it beyond describing it as one of the leading open-source models competitive with commercial frontier models. That makes the comparison Maestro against its own untrained base, which is a legitimate way to measure whether post-training worked and not a way to measure whether Maestro beats the model a customer would otherwise use. Both are useful questions. Only the second decides a purchase, and Cadence has not answered it.

Why token economics is the real argument

The commercial case is stronger than the benchmark case, and Cadence executives make it plainly. Paul Cunningham, a senior vice president, told Tom’s Hardware that agent costs have really started to explode, and that the natural response is to move more of the agents’ iterating into the weights of the models themselves. The reasoning is arithmetic: an autonomous chip design task such as root-causing a regression failure or converging timing and power runs for a long time and invokes a model repeatedly, and pricing every step at frontier-model rates makes autonomy uneconomic at production scale.

That is the argument the five-times token efficiency claim is meant to support, and it is the right argument for this market. It also explains the deployment options. Maestro runs on Cadence’s cloud, on public clouds, or entirely inside a customer’s data centre, and customers can post-train it on their own designs using Cadence’s fine-tuning harness, potentially on their own GPUs and network. Cadence is selling a cheaper way to run agents at volume and a way to keep the training data at home, which are two answers to two different objections.

The autonomy claim deserves a note because it explains why a specialised model is needed at all. Cadence claimed Level 5 autonomy for ChipStack in June, which in this context means an agent that completes a task without human intervention rather than one that suggests next steps. An agent working at that level runs for hours, makes hundreds of decisions and needs a reward signal at each one. A frontier model can supply the reasoning but not the verification, and a human reviewer cannot keep pace. The solver is what makes autonomy economical rather than merely possible.

The duopoly splits

The strategic picture is the part that will outlast the announcement. Cadence and Synopsys dominate electronic design automation, the software that places billions of transistors within power, performance and cost limits, and both now race to let agents operate those tools. Their model strategies have diverged within a month. Synopsys tied itself to a single frontier lab with a revenue-sharing arrangement and hosted inference. Cadence built a portfolio it can ship to customers, post-train locally and route across, and Cunningham frames it as model-agnostic on the grounds that there are more model providers than there are chip design software vendors.

NVIDIA’s role deserves a note because it cuts both ways. It supplies Nemotron as a base and OpenShell for agent sandboxing and governance, and it also works with Synopsys on agentic design. That is a supplier collecting from whichever EDA vendor performs, and it is also the behaviour of the most sophisticated chip design customer in the world, which uses Cadence’s tools for its own silicon and still needs the vendor’s environment for verified rewards. The dependency runs in both directions, and neither side is likely to say so.

What to watch

Three markers will show whether Maestro changes anything. The first is whether Cadence publishes a benchmark against a named frontier model rather than its own base, because that is the comparison a buyer needs. The second is production evidence: Socionext is deploying InnoStack and expects up to five times productivity gains, Silicon Labs credits ChipStack with faster root-cause analysis, and both are watching Maestro. Named results from those two would settle more than any percentage. The third is Synopsys’s counter, since Autopilot and AgentEngineer are due toward general availability by year end.

What it signals

The announcement marks the point where the EDA duopoly stopped treating AI as a feature and started treating model ownership as strategy. Cadence‘s bet is that chip design is a vertical whose data cannot leave the building, and that the winning position is to own the models, the solvers and the reward loop rather than to rent intelligence from a lab. Synopsys‘s bet is that a frontier lab moves faster than a post-training programme. Both will be tested by the same thing, which is whether a design team can point to a chip that taped out faster because of it. That is a high bar and the right one, since tape-out is where the money and the schedule actually sit, and where a design either ships or does not.

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